1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a floating gate and a control gate which is formed to overlap the floating gate through a tunneling oxide film covering the floating gate, and a method of manufacturing it, and more particularly to technology for preventing a reduction in the erasure efficiency when data erasure is repeated by extracting charges (electrons) stored in the floating gate towards the control gate, thereby extending the operation life (cycle life) of a memory cell.
2. Description of the Related Art
In an electrically erasable non-volatile semiconductor memory device composed of memory cells each consisting of a single transistor, particularly a programmable ROM (EEPROM: Electrically Erasable and Programmable ROM, also referred to as xe2x80x9cflash memoryxe2x80x9d), each memory cell consists of a transistor in a double-gate structure having a floating gate and a control gate. In such a memory cell transistor in a double gate structure, write of data is performed by accelerating hot electrons generated on the side of a drain region so as to be injected into the floating gate. Erasure of data is performed by extracting charges from the floating gate to the control gate through F-N tunneling (Fowler-Nordheim tunneling).
FIG. 10 is a plan view of a memory cell portion of a non-volatile semiconductor memory device having a floating gate. FIG. 11 is a sectional view taken in line X1xe2x80x94X1 in FIG. 10. The memory cell portion adopts a split gate structure in which a control gate is arranged in parallel to a floating gate.
A plurality of element isolation films 2 of a thick LOCOS oxide film selectively formed by LOCOS (Local Oxidation of Silicon are formed in stripes on a surface area of a P-type semiconductor substrate 1 so that element areas are sectioned from one another. Floating gates 4 are formed on the semiconductor substrate 1 so that each of them extends between adjacent element isolation films 2 through an oxide film 3A. The floating gate 4 is arranged individually in each memory cell. By selective oxidation, a selective oxide film 5 on the floating gate 4 is formed to be thicker in the central area and have an acute corner on the edge thereof so that concentration of an electric field is likely to occur at the edge of the floating gate 4 during data erasure.
On the semiconductor substrate 1 on which the plurality of floating gates 4 are arranged, control gates 6 are arranged so as to correspond to the respective columns of the floating gates 4 through the tunneling oxide film 3 integrated to the oxide films 3A. The control gate 6 partially overlaps the floating gate 4 and the remaining portion thereof abuts on the semiconductor substrate 1 through the oxide film 3A. The floating gates 4 and the control gates 6 are arranged so that they are symmetrical from each other in adjacent columns.
An N-type drain region 7 and a N-type source region 8 are formed in the substrate areas between the control gates 6 and between the floating gates 4. The drain region 7 is individually surrounded by the element isolation films 2 between the control gates 6, whereas the source region 8 extends along the control gate 6. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.
A metallic wiring 10 of aluminum alloy is arranged on the control gate 6 in a direction perpendicular to the control gate through an interlayer insulating film 9. The metallic wiring 10 is connected to the drain region 8 through a contact hole 11. Each control gate 6 serves as a word line whereas the source region 8 extending along the control gate 6 serves as a source line. The metallic wiring 10 connected to the drain region 7 serves as a bit line.
In the case of the memory cell transistor in a double gate structure, the xe2x80x9conxe2x80x9d resistance between the source and drain varies according to the quantity of charges injected into the floating gate 4. Therefore, by selectively injecting the charges into the floating gate 4 so that the xe2x80x9conxe2x80x9d resistance of a specific memory cell transistor is varied, a difference thus produced in the operation characteristic of each memory cell transistor is correlated with the data to be stored.
The respective operations of write, erasure and read of data in the non-volatile semiconductor memory device can be performed in the following manner. In the write of data(data writing operation), the potential of the control gate 6 is set at 2 V; the potential of the drain region 7 is set at 0.5 V and the high potential of the source region 8 is set at 12 V. In this case, the potential of the floating gate 4 is elevated to about 9 V because of the difference in the capacitive couplings between the control gate 6 and floating gate 4 and between the floating gate 4 and substrate (source region 8) (i.e. capacitance between the control gate 6 and floating gate 4 less than capacitance between the floating gate 4 and substrate). Thus, the hot electrons generated in the vicinity of the drain region are accelerated toward the floating gate 4 and injected into the floating gate 4 through the oxide film 3A, thereby making the write of data.
In the erasure of data(data-erasing operation), the potential of each of the drain region 7 and source region 8 is set at 0 V and that of the control gate 6 is set at 14 V. In this case, the charges (electrons) pass through the tunnelling oxide film 3 from the acute portion at the corner of the floating gate 4 by the F-N (Fowler-Nordheim tunneling) conduction so that they are discharged into the control gate 6, thereby making the erasure of data.
In the read of data(data-reading operation), the potential of the control gate 6 is set at 4 V; that of the drain region 7 is set at 2 V and that of the source region 8 is set at 0 V. In this case, if the charges (electrons) have been injected in the floating gate 4, the potential at the floating gate 4 becomes low. Therefore, no channel is formed beneath the floating gate 4 so that a drain current does not flow. In contrast, if the charges (electrons) have not been injected in the floating gate 4, the potential of the floating gate 4 becomes high. Therefore, the channel is formed beneath the floating gate 4 so that the drain current flows.
FIG. 9 is a graph showing a measurement result (indicated by one-dot chain line) of a cycle life (number of times of the erasure/write of data: E/W Cycle) in a conventional device having the above configuration. As seen from the graph, the accumulated failure rate (%) increases with an increase of the E/W cycle. Incidentally, the xe2x80x9cfailurexe2x80x9d in this case refers to the operation life of a memory cell when the cell current lowers to a decidable level (e.g. when the memory cell current of the memory cell in the erasure state becomes 30 xcexcm which is 30% of the initial value of 100 xcexcm).
As seen from the graph, in the conventional non-volatile semiconductor memory device, when the number of times of E/W of data reaches about 70,000 times, the accumulated failure rate reaches 100%.
A general programmable memory requires the E/W cycle of about 100,000 times, and that of 70,000 times is insufficient. Therefore, it has been demanded to increase the number of times of the E/W cycle.
As a result of analysis by the inventors of the present invention, it has been found that the material of the interlayer dielectric film formed on the memory cell transistor is correlated with the cycle life.
Specifically, in an device configuration in which a relatively large level difference occurs because the control gate overlaps the floating gate like the non-volatile semiconductor memory device according to the present invention, an interlayer dielectric film 9 subjected to an etch back step of a SOG (Spin On Glass) film is formed.
The inventors have supposed that the cycle life is influenced by the fact that H or OH contained in the SOG film will be diffused and trapped by the tunneling oxide film.
The plasma hydrogen (H2)when a plasma silicon nitride (SiN) film used as a final passivation film is deposited by the plasma LPCVD may influence the cycle life.
An object of the present invention is to provide a non-volatile semiconductor memory device capable of improving the operation life of a memory cell, and its manufacturing method.
Another object of the present invention is to provide a high quality non-volatile semiconductor memory device free from film peeling-off and its manufacturing method.
The non-volatile semiconductor memory device according to the first aspect of the present invention is characterized by comprising: a floating gate formed on a semiconductor substrate having a first conduction type; a tunneling dielectric film covering the floating gate; a control gate formed to have a region overlapping the floating gate through the tunneling dielectric film; diffused regions formed on a surface of the semiconductor substrate adjacent to the floating gate and the control gate, the diffused region having a second conduction type opposite to the first conduction type; a silicon nitride film which covers at least a portion of an area where a memory cell region is to be formed; and a wiring connected to the diffused region through an interlayer dielectric film formed on the silicon nitride film.
In one embodiment in accordance with our invention, the interlayer dielectric film is a dielectric film containing at least an SOG film.
In another embodiment in accordance with our invention, the silicon nitride film is formed to cover an entire surface of the semiconductor substrate.
In another embodiment in accordance with our invention, the silicon nitride film is formed to cover an entire surface of the semiconductor substrate exclusive of an outer periphery thereof.
In another embodiment in accordance with our invention, the silicon nitride film is selectively formed on a prescribed region of an area where the memory cell is to be formed.
In another embodiment in accordance with our invention, the silicon nitride film is formed to cover the floating gate and control gate on the side of one diffused region.
In another embodiment in accordance with our invention, the silicon nitride film is formed to cover at least an end portion of the control gate which is located on the floating gate.
In another embodiment in accordance with our invention, the silicon nitride film is formed in a belt shape so as to cover at least an area extending from a source region to the end of the control gate which is located on the floating gate.
In another embodiment in accordance with our invention, the silicon nitride film is selectively formed so as to cover the region exclusive of an area where a drain contact is to be formed and periphery thereof.
The method for manufacturing a non-volatile semiconductor memory device according to the second aspect of the present invention is characterized by comprising the steps of: forming a gate dielectric film on a Si substrate having a first conduction type; forming floating gates on the gate dielectric film; forming a tunneling dielectric film so as to cover the floating gates; forming control gates on the tunneling dielectric film so as to have a region overlapping the floating gates through the tunneling dielectric film; forming a first diffused region on a surface of the semiconductor substrate so as to be located between the adjacent floating gates, the diffused region having a second conduction type opposite to the first conduction type; successively stacking forming a dielectric film and a silicon nitride film on the entire surface of the Si substrate; patterning the silicon nitride film so as to cover the floating gate and control gate on the side of the first diffused region and to expose a second diffused region; anisotropically etching the dielectric film so as to cover the floating gate and control gate on the side of the first diffused region and to expose the substrate surface on the side of an area where the second diffused region is to be formed and patterning the dielectric film to form a side wall spacer film covering the side wall of the control gate on the side of the area where the second diffused region is to be formed; forming the second diffused region having the second conduction type on the surface of the Si substrate; forming a flattened interlayer dielectric layer inclusive of a step of etching back an SOG film formed on the entire surface of the substrate; and making a wiring in contact with the second diffused region through an hole made in the interlayer dielectric layer.
The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.